The present invention relates, in general, to the field of integrated circuit memory devices and those devices incorporating embedded memory. More particularly, the present invention relates to a high-speed, static random access memory (SRAM) compatible, high availability memory array and method employing synchronous dynamic random access memory (DRAM) in conjunction with a data cache and separate read and write data registers and tag blocks, hereinafter sometimes referred to as a high-speed SCRAM (Static Compatible Random Access Memory).
SRAM is a type of memory technology which can maintain data without needing to be refreshed for as long as power is supplied to the circuit (i.e. “static”). This is, in contrast to DRAM which must be refreshed many times per second in order to maintain its data (i.e. “dynamic”). Among the main advantages of SRAM over DRAM is the fact that the former doesn't require refresh circuitry in order for it to maintain data, unlike the latter. For this and other reasons, the data access speed of SRAM is generally faster than that of DRAM. Nevertheless, SRAM is, on a byte-for-byte storage basis, more expensive to produce than DRAM due primarily to the fact that SRAMs take up much more on-chip area than DRAMs since SRAM is generally made up of four, six or even more transistors per memory cell. A DRAM cell, in contrast, generally comprises one transistor and one capacitor.
As mentioned previously, DRAM is constructed such that it only maintains data if it is fairly continuously accessed by refresh logic. Many times per second, this circuitry must effectively read the contents of each memory cell and restore each memory cell regardless of whether the memory cell is otherwise currently being accessed in a data read or write operation. The action of reading and restoring the contents of each cell serves to refresh the memory contents at that location.
Among the advantages of DRAMs are that their structure is very simple and each cell typically comprises but a single small capacitor and an associated pass transistor. The capacitor maintains an electrical charge such that, if a charge is present, then a logic level “1” is indicated. Conversely, if no charge is present, then a logic level “0” has been stored. The transistor, when enabled, serves to read the charge of the capacitor or enable writing of a bit of data to it. However, since these capacitors are made very small to provide maximum memory density and they can, under the best of circumstances, only hold a charge for a short period of time, they must be continually refreshed.
In essence, the refresh circuitry then serves to effectively read the contents of every cell in a DRAM array and refresh each one with a fresh “charge” before the charge leaks off and the data state is lost. In general, this “refreshing” is done by reading and restoring every “row” in the memory array whereby the process of reading and restoring the contents of each memory cell capacitor re-establishes the charge, and hence, the data state.
Consequently, it would be highly advantageous to provide a memory architecture which exhibited the memory density advantages of DRAM while nonetheless being able to provide memory access times approaching that of SRAM through the coordination of refresh operations (hidden refresh) so as not to impede normal memory read/write data access. In this regard, a number of ways of hiding DRAM refresh operation have heretofore been proposed for both synchronous DRAMs (SDRAMs; those memories in which operation of the memory is controlled by “valid” or “invalid” signals relative to the edges of a clock) and asynchronous DRAMs in which no clock synchronization is utilized.
Asynchronous Memory Refresh Hiding Techniques:
An article entitled “1-Mbit Virtually Static RAM”, Nogami et.al., IEEE Journal of Solid-State Circuits, Vol. SC-21, No. 5, October 1986 pp. 662-667 describes a particular method for hiding refresh operations in an asynchronous DRAM, but as shown in Table IV at page 666m it is not completely compatible with (asynchronous) SRAMs. In addition a significant access time and cycle time penalty is incurred in its implementation.
A different article entitled: “4 Mb Pseudo/Virtually SRAM”, Yoshioki, et.al., 1987 IEEE International Solid-State Circuits Conference, Digest of Technical Papers pp. 20-21 and 1987 ISSCC pp. 320-322 describes another method for hiding refresh that effectively increases the address access time from 60 nS to 95 nS, resulting in an unacceptably large performance penalty.
U.S. Pat. No. 6,625,077 issuing Sep. 23, 2003 to Chen for: “Asynchronous Hidden Refresh of Semiconductor Memory” describes a method for hiding refresh operations in an asynchronous DRAM by “stretching” all read or write cycles. The exact performance penalty incurred through implementation of the technique is not disclosed but would be significant.
Similarly, U.S. Pat. No. 6,445,636 issuing Sep. 3, 2003 to Keeth et al. for: “Method and System for Hiding Refreshes in a Dynamic Random Access Memory” describes a method for hiding DRAM refresh by doubling the number of memory cells, thus effectively doubling the area required. The method indicated incurs an unacceptably large cost penalty.
Synchronous Memory Refresh Hiding Techniques:
U.S. Pat. No. 5,999,474 issuing Dec. 7, 1999 to Leung et al. for “Method and Apparatus for Complete Hiding of the Refresh of a Semiconductor Memory” (hereinafter sometimes referred to as the “'474 patent”) describes a method for hiding refresh in what appears to be an SDRAM (this is inferred by the CLK signal in FIG. 4) utilizing among other things a static RAM (SRAM) cache of the same size as one of the DRAM subarrays. Since, as previously noted, SRAM cells are much larger than DRAM cells, the physical size of the SRAM cache will be a significant penalty in implementing the method shown. U.S. Pat. No. 6,449,685 also to Leung issuing Sep. 10, 2002 for “Read/Write Buffers for Complete Hiding of the Refresh of a Semiconductor Memory and Method of Operating Same” (hereinafter sometimes referred to as the “'685 patent”) addresses the issue of the size of an SRAM cache by replacing it with two DRAM caches of the same size. The two DRAM caches are somewhat misleadingly referred to as a write buffer and read buffer in FIG. 5, but each buffer has the same capacity as the SRAM cache shown in FIG. 1, so they are, in reality, caches.
In both the '474 and '685 patents, a cache may contain data from multiple subarrays at any one time. This imposes a size requirement on the tag SRAM memory that is equal to the number of words (a word being equal to the number of bits per address) in a subarray multiplied by (2+the number of bits required to uniquely address each subarray). A further fundamental limitation on the methods described is that the SRAM cache implements a write-back policy, such that all write data is initially written to the SRAM cache before being written to the memory banks, and all read data provided to the external data bus is stored in the SRAM cache. Since the data written to cache will be eventually written to the subarrays, the writes to cache consume power that would not be necessary for a DRAM not hiding refresh. Since the cache is expected to consume more power than a DRAM subarray per access, this write to cache before writing to a subarray is expected to more than double array power for writes. For random reads, 63 of 64 reads will be misses. Reading the subarray and writing to the cache is also expected to more than double the power 63 of 64 times. U.S. patent application Ser. No. 2003/0033492 to Akiyama et al. for: “Semiconductor Device with Multi-Bank DRAM and Cache Memory is very similar to that described in the '685 patent.
In general, the primary deficiencies of the known techniques for hiding refresh operations in asynchronous and synchronous DRAMs are that either an SRAM cache or two DRAM caches are required in addition to a tag capacity larger than might be desired. Disclosed in the aforementioned patent application incorporated by reference herein is a static random access memory (SRAM) compatible, high availability memory array and method employing synchronous dynamic random access memory (DRAM) which enables 100% memory system availability in a memory array comprising DRAM memory cells with only a single DRAM cache and a smaller tag than utilized in conventional techniques.